A 77.3-dB SNDR 62.5-kHz Bandwidth Continuous-Time Noise-Shaping SAR ADC With Duty-Cycled G_m-C Integrator

This article presents a first-order continuous-time (CT) noise-shaping successive-approximation-register (NS-SAR) analog-to-digital converter (ADC). Different from other NS-SAR ADCs in literature, which are discrete-time (DT), this ADC utilizes a CT Gm-C integrator to realize an inherent anti-aliasing function. To cope with the timing conflict between the DT SAR ADC and the CT integrator, the sampling switch of the SAR ADC is removed, and the integrator is duty cycled to leave 5% of the sampling clock period for the SAR conversion. Redundancy is added to track the varying ADC input due to the absence of the sampling switch. A theoretical analysis shows that the 5% duty-cycling has negligible effects on the signal transfer function (STF) and the noise transfer function. The output swing and linearity requirements for the integrator are also relaxed thanks to the inherent feedforward path in the NS-SAR ADC architecture. Fabricated in 65-nm CMOS, the prototype achieves 77.3-dB peak signal-to-noise and distortion ratio (SNDR) in a 62.5-kHz bandwidth while consuming 13.5μ W, leading to a Schreier figure of merit (FoM) of 174.0 dB. Moreover, it provides 15-dB attenuation in the alias band.</p

A 2.98pJ/conversion 0.0023mm2 Dynamic Temperature Sensor with Fully On-Chip Corrections

Nowadays, many battery-operated SoCs for loT and environmental monitoring applications are equipped with temperature sensors. In these miniaturized systems, power and area are two critical concerns. One challenge for temperature sensors is that they are sensitive to process corners and random mismatch. Generally, a 2-point trim and systematic non-linear error removal are required, especially for resistor-based sensing front-ends with two types of resistors, whose spread is partially uncorrelated [1], [2]. These corrections are done off-chip and digitally in most publications. In particular for low power sensors, they may consume more power and area than the sensor itself when integrated on-chip [3]. This work presents a resistive temperature sensor that integrates on-chip analog offset, gain and non-linearity correction techniques, while keeping state-of-the-art power and size performance. The prototype consumes 2.98pJ/conversion with an area of 0. 0023textmm 2 including all the correction techniques and achieves +0.7/-0.6 circC inaccuracy.</p

A 2.2 fJ/Conversion-Step 9.74-ENOB 10 MS/s SAR ADC With 1.5×Input Range

This brief presents a 10.5-bit 10 MS/s successive-approximation-register (SAR) analog-to-digital converter (ADC) with 1.5times input range (IR). By pre-setting and resetting the most significant bit (MSB) of the digital-to-analog converter (DAC) to shift the input signal accordingly, the input range of the ADC is enhanced by a factor of 1.5. This effectively relaxes the noise requirement and thus improves the power efficiency of the ADC. The prototype implemented in 65-nm CMOS technology achieves a signal-to-noise-and-distortion ratio (SNDR) of 60.37 dB and a spurious-free dynamic range (SFDR) of 82.2 dB. It consumes 18.65~mu text{W} at 10 MS/s with a 0.8V supply and only occupies an area of 0.0013 mm2. The resulting Walden figure of merit (FoM _{W} ) is 2.2 fJ/conversion-step.</p

Small-Area SAR ADCs With a Compact Unit-Length DAC Layout

This brief presents four small-area SAR ADCs with a resolution from 8 to 11 bits. Two area-saving techniques are utilized. First, the DAC layout is implemented with custom designed unit-length capacitors, which are optimized for each resolution to minimize the chip area. Second, dynamic logic is applied to the 8-bit design to further reduce the number of transistors and save area. Fabricated in 65 nm CMOS, the 8/9/10/11-bit SAR ADCs only occupy 20times 21,,mu text{m} , 20times 36,,mu text{m} , 36times 36,,mu text{m} and 36times 36,,mu text{m} , respectively. At 10 MHz sampling rate, their measured ENOB is 7.5, 8.3, 9.1 and 9.8 bits with an SFDR of 65.4 dB, 67.4 dB, 78.0 dB and 76.5 dB, respectively. Compared to prior-art, these designs achieve the smallest areas for the achieved ENOBs.</p

A 10-bit 4 MS/s SAR ADC with Fully-Dynamic Duty-Cycled Input Driver

This paper presents a duty-cycled input driver for a SAR ADC. Being a discrete-time system, the SAR ADC requires an accurate input signal only at its sampling moment. This motivates the use of a duty-cycled input driver which can be turned off during the conversion phase to save power. In this way, the power consumption of the SAR ADC together with its input driver becomes fully dynamic. This idea is applied to a 10-bit 4 MS/s SAR ADC with unity-gain input drivers. Fabricated in 65 nm CMOS, the prototype achieves 8.9 ENOB and 69.9 dB SFDR while consuming 35.0 µW. This leads to a Walden FoM of 18.3 fJ/conversion-step for the ADC including driver.</p

A SAR ADC with Reconfigurable Delay and Redundancy to Relax the Reference Driver

This work presents a reconfigurable delay and redundancy technique, which relaxes the reference driver requirements for a charge-redistribution SAR ADC. By selectively adding delay to the most critical SAR cycle, the overall speed of the ADC is only slightly degraded, while the output impedance of the driver or the amount of decoupling capacitance can be reduced substantially. In a simulated 10-bit 10 MS/s SAR ADC prototype, the proposed technique reduces the decoupling capacitance by 16× while maintaining 59.2 dB SNDR and 71.2 dB SFDR at a power consumption of 32 mu mathrm{W}. The estimated area is 0.002 mm2 including decoupling capacitors.</p

A 0.0033 mm²3.5 fJ/conversion-step SAR ADC with 2× Input Range Boosting

This paper proposes an input range boosting technique for successive-approximation-register (SAR) analog-to-digital converters (ADC). By performing a pre-comparison and switching the DAC accordingly, the input range of a SAR ADC can be doubled with limited power and area overhead. This effectively improves the power efficiency by relaxing the noise requirement and improves the area efficiency by using less DAC capacitors. A prototype ADC is fabricated in 65 nm CMOS and occupies an area of 0.0033 mm2. It consumes 34.06μW at 10 MHz sampling rate from a 1 V supply. The measured SNDR is 62 dB for a 5 MHz bandwidth, resulting in a Walden figure of merit (FoMW) of 3.28 fJ/conversion step.</p

A 7.3-μ W 13-ENOB 98-dB SFDR Noise-Shaping SAR ADC With Duty-Cycled Amplifier and Mismatch Error Shaping

This article presents a second-order noise-shaping successive-approximation-register (SAR) analog-to-digital converter (ADC) that employs a duty-cycled amplifier and digital-predicted mismatch error shaping (MES). The loop filter is composed of an active amplifier and two cascaded passive integrators to provide a theoretical 30-dB in-band noise attenuation. The amplifier achieves 18\times gain in a power-efficient way thanks to its inverter-based topology and duty-cycled operation. The capacitor mismatch in the digital-to-analog converter (DAC) array is mitigated by first-order MES. A two-level digital prediction scheme is adopted with MES to avoid input range loss. Fabricated in 65-nm CMOS technology, the prototype achieves 80-dB peak signal-to-noise-and-distortion-ratio (SNDR) and 98-dB peak spurious-free-dynamic-range (SFDR) in a 31.25-kHz bandwidth with 16\times oversampling ratio (OSR), leading to a Schreier figure-of-merit (FoM) of 176.3 dB and a Walden FoM of 14.3 fJ/conversion-step.</p

Noise-Shaping SAR ADCs: From Discrete Time to Continuous Time

Noise-shaping (NS) SAR ADCs become popular recently, thanks to their low-power and high-resolution features. This article first summarizes and benchmarks different discrete-time (DT) NS-SAR implementations in literature. An open-loop duty-cycled residue amplifier is selected as a power-efficient solution to realize high residue gain. Then, a digital-predicted mismatch error shaping technique is introduced to improve the DAC linearity. The proposed DT NS-SAR ADC achieves 80 dB SNDR and 98 dB SFDR in a 31.25 kHz bandwidth while consuming 7.3 μW. Next, the NS-SAR architecture is extended from DT operation to continuous-time (CT) operation. The ADC sampling switch is removed, and the loop filter is duty cycled to realize the CT NS-SAR operation. Compared to DT designs, the CT NS-SAR ADC is easy to drive and has an inherent anti-aliasing function. As a proof of concept, the proposed CT NS-SAR ADC achieves 77 dB SNDR and 86 dB SFDR in a 62.5 kHz bandwidth with a power consumption of 13.5 μW